3-D vertically integrated chip, part 2

This 3-D vertically integrated photon imaging chip, better known as a VIPIC, comprises two interconnected layers of electronics. Designed by PPD’s ASIC Development Group at Fermilab, which also organized its fabrication together with others in the HEP community, the roughly 6.5 mm-by-5.5 mm chip was assembled with a pixelated sensor, which is a source of charge signals arising from absorbed radiation. See part 1. The group successfully met the challenge of mounting a sensor on an already multilayered chip, using solder bump bond technology and working with an industrial partner. By taking advantage of the 3-D design, engineers design chips that can process information from particle collisions or X-ray absorptions more efficiently than if the functionality were implemented in the larger footprint of a classical 2-D chip. The assembly below is ready for tests. Photo: Fermilab ASIC Group